Hi I've had pretty good luck with Quartus setting up delay relationships and optimizing for them. You are correct that you do get speed variations from the slow model to the fast model. Getting it all to work out is usually a two step process. Find the delay clusters and then shove the outliers towards the center of the cluster. If you make a big change it's back to the start again. You wind up with 7.3 ns +/- 0.5 one time and next time after a big change it'll be 8.7 ns +/- 0.5 Either way you got them set up to 0.5. I suspect there's a way to automate it, but it's easy enough to do by hand for a couple dozen paths.
Generally with something like a divider, you just want to make sure that everything going out is all timed the same to the pins of the chip. I would be very surprised if any of the tools had trouble with that. It's pretty much what they were built to do. Bob On Mar 20, 2010, at 3:35 PM, Hal Murray wrote: > >> When you run a design on a CPLD (or a FPGA) the design tool optimizes cute >> things like fanout and timing. You can also have it optimize delay to >> circuit nodes. That allows you to come up with outputs that have a specific >> delay relationship. > >> From my experience, "specific delay relationship" is probably pushing it. > > The Xilinx tools are really setup for building synchronous logic. They are > very good at calculating the max delay from A to B. > > On the other hand, they are almost useless for the min or typical delays. > > One complication is that sometimes they ship fast parts marked as a slow > grade. That's more likely with mature products. When the fab line is well > tuned they don't make any slow chips. > > About the best you can do is something like: > If this chunk of a design is the same as that one then the delays will > probably be close. "Same" includes logic, layout, and routing. They will > (probably) track closer if they are in the same chip. > > -------- > > Internally, the Xilinx tools don't even calculate the min delays. They do > works-by-design rather than checking hold times. You can explain it by > saying "0 hold time", but what's really going on is that the min prop times > have to cover the hold time and clock skew. Note that prop times and hold > times track temperature and voltage so the worst case (fastest) prop time > happens when you don't need the worst case hold times. > > I seem to remember that I checked a data sheet many years ago. It was a > typical FF, probably something like an x374. The min clock-to-out was not > enough to cover the hold time. > > I just checked a modern data sheet. They didn't even have any numbers for > min clock-to-out. > > Hold times are ugly. > > > -- > These are my opinions, not necessarily my employer's. I hate spam. > > > > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
