> I would like to generate a DS-1 timing reference from 10 MHz, e.g a > T-bolt. Thought someone here might be able to suggest a starting point.
One approach is a PLL. You will have to divide 1.544 MHz by 193 and 10 MHz by 1250. If you want to use the TAPR Clock-Block, I think you will need something like a divide by 10 between the 10 MHz and the Clock-Block to get the numbers within range. I wonder if you could use a VCXO and fit all the logic in a tiny micro. It would probably need a few external parts to filter the PWM output. Maybe the filtering inside the VCXO would be good enough. Another approach is to use a DDS. Analog Devices makes the whole thing in one package, but the numbers don't work out exactly. How close to you need to be? With a 32 bit (binary) adder, you get 1544000.001158 MHz. With 48 bits you get 1543999.999999989825. But you don't have to use a binary adder. You have 10000000 Hz and you want 1544000 Hz, so you need to multiply by 1544000 and divide by 10000000. That reduces to 193 / 1250. So add 193 each cycle using modulo 1250 addition. Each time it overflows, kick out a pulse. If you want a square wave output, divide by 625 and toggle the output on each overflow. That sort of logic fits well in a FPGA/CPLD. That will give you a clock that's locked to your input clock but with lots of jitter. (up to 1/2 clock off in each direction, so 100 ns peak-to-peak) You can run that through a low pass filter and/or feed the top bits into a sine table and on to a DAC. Note that isn't the standard ROM. You have to make a new table for each modulus and if you are using standard ROMs with binary addressing you will waste up to 1/2 of each ROM. -- These are my opinions, not necessarily my employer's. I hate spam. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
