At 19:01 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
At 08:30 +1200 14-08-2010, Bruce Griffiths wrote:
Using a synchroniser allows the TAC output range to be combined
with the coarse timestamp derived by sampling a counter clocked by
the same clock as the synchroniser.
I think we're looking at it from two different angles.
What I read from your description is close to the traditional
architecture such as used in the HP5335A, with a counter running at
the system clock frequency for coarse measurement and a TAC to
measure the remainder. What I'm planning to do is more akin a
traditional PLL, with the TAC as the Phase Detector. For this to
work I assume that a coarse FLL (using a counter) has already
brought the oscillator within lock range. Is there any reason that
method won't work, or can trivially be made to work better?
Having a wide TAC range means that its resolution and noise depends
critically on that of the ADC.
Since some ADCs embeded within processor dont have true 12 bit
performance this may limit the TAC resolution/noise to several
nanosec rather than the desired 1ns or better.
No, the TAC range would only be wide enough to cover the expected
spread of valid PPS pulses from the GPS (say +/-500ns...+/-1us).
(I've thought a bit more about what you proposed, ie using the TAC to
measure synchronizer delay. Problem is I'd like to use the
timestamping counter that's internal to the CPU, and I see no way of
getting at the output of its built-in synchronizer. This could of
course be fixed by using an external timestamping
counter/synchronizer, but that seems like a bit of a waste of
resources).
(The regenerated PPS output will indeed be derived from and
synchronous with the VCXO/OCXO. It is also my intention to have the
OCXO clock the microcontroller, either directly or through a
prescaler, depending on whether the XO runs higher or lower than
the max CPU clock).
That ensures that all intermod products are harmonically or
submultiples of the OCXO frequency.
Indeed. I prefer knowing where my birdies are (and preferably placing
them where they do the least harm), rather than having them drift
over time, frequency and temperature.
The output compliance of your four transistor current mirror is
limited to around 1.3V or so before the onset of saturation or
gross nonlinearity.
It's actually better than that, from what I can see from
simulations and measurements. If the transistor currents are close
to equal and the ramp rate isn't too high, output current stays
within 1% up to ~1V, and the mirror saturates at 0.6-0.7V. This is
with common small-signal transistors with an fT of a few hundred
MHz.
Really?
There are 2xVbe + 1x diode drop to subtract from 3.3V ie somewhere
from 1.8V -2.4V leaving a ramp amplitude of 1.5V to 1.1V depending
on temperature and transistor current.
That's what I thought when I first saw it and started counting
junctions, but it's actually quite a bit better than that as the
cross-coupling of the transistors steers current from saturating
transistors into the bases of the opposing CE transistor. I found it
in Barrie Gilbert's chapter on Bipolar Current Mirrors in the book
"Analogue IC Design: the current-mode approach"; Google Books has a
preview of much of this chapter.
I've tried it in the simulator and on the bench, and it works quite
well. If you want to test it I suggest increasing the current source
to 10mA, the cap to 10nF and starting with 150R for R1/R2 plus 10R
emitter resistors for the CE transistors. I've tested it with the
common European BC5xx/BC8xx-types, but LTSpice seems to like it with
2N3906s too. In that configuration, the ramp stays within +/-150uV of
a linear approximation over a ramp range between 0 and 2V when
ramping at 1V/us, which corresponds to +/-0.6LSB for a 12-bit ADC.
[I should probably make a sketch of the entire GPSDO and post it]
Yes that would be useful as details can often be important.
I have to leave now, will do so when I get back.
Thanks,
JDB.
--
Years from now, if you are doing something quick and dirty,
you imagine that I am looking over your shoulder and say to
yourself, "Dijkstra would not like this," well that would be
immortality for me. -- Edsger Dijkstra, 1930 - 2002
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
