One can estimate the resultant jitter from the input slew rate and the
circuit noise and bandwidth.
Too much bandwidth with a slow input slew rate increases the jitter
substantially over that possible with an optimal circuit.
Bruce
Robert LaJeunesse wrote:
Assuming a transformer coupled input (with biasing via a secondary center tap)
why not use a fast differential PECL to CMOS level translator? For example, the
IDT ICS508 will take 0.3 to 1.0 V p-p input and give 2.5, 3.3, or 5 V swing on
the output. The chip works down to DC and keeps the duty cycle in the 40%-60%
window up to 250MHz (at 3.3V out). Jitter and noise is not spec'd however.
To increase the noise immunity with a relatively slow 10MHz sine source I'd look
at boosting the amplitude with the transformer, then clipping with balanced
series resistors and back-to-back diodes so the translator sees a higher dV/dT
on its inputs.
Might want to look in some old Motorola ECL appnotes for other possible schemes.
Bob
________________________________
From: jimlux<jim...@earthlink.net>
To: Discussion of precise time and frequency measurement<time-nuts@febo.com>
Sent: Wed, December 8, 2010 10:31:08 AM
Subject: [time-nuts] reference oscillator input circuit
I'm looking for suggestions on a general circuit that can be used to receive an
external frequency reference (nominally a real clean sine wave at, say, 10 MHz,
although up to 100 MHz is possible) and turn it into a "real clean" square
wave. Galvanic isolation is a plus (a transformer or capacitor would probably
do that).
I was thinking about rummaging through the schematics for test equipment
reference inputs (since they've already "solved" the problem, eh?), but any
other ideas would be welcome.
I've scanned the archives of time-nuts, and while we have a fair amount of
discussion on how to square up the 1Hz (or 100Hz) in a phase noise/ADEV setup,
not so much on what to do with the 10 MHz. Rick has commented that you don't
want to use a comparator. I have the papers by Dick, et al, and Collins, as well
as all the others.. they tend to be looking at the low frequency problem,
although the analysis is certainly applicable.
I don't know that I'm looking for the whole multiple limiting stages scheme in
any case.
Oh, as far as performance.. Say the need is to not horribly degrade a good
quality crystal oscillator... here's a typical set of specs:
76 MHz
1Hz<-90dBc
10Hz<-110dBc
100Hz<-120dBc
1k-100k<-125dBc
Adevs of the oscillator run from 5E-12 at 0.1 sec, down to 1E-12 at 10 sec, and
back up to 2 E-12 at 1000sec.
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