My general solution to generating clock frequencies of any frequency
is to
take a middle frequency from the divider chain (say 10kHz) and feed
it into a PLL
chip with a divider (say 3 or 6 using a Johnson counter which resets)
in the feedback loop.
This multiplies the VCO output by 3 (30kHz or 60kHz) which will then
divide down to 60Hz
with very little phase noise. The only difficulty is the need for a
reset that is synchronised
with the PPS signal. (use a D latch or two)
cheers, Neville Michie
Recently I bought a Efratom Ru frequency standard from eBay and a
frequency
divider chip that makes 1MHZ,100KHZ,25KHZ,10KHZ,100HZ and a 1HZ
output.
Today I thought of a way to make a nice 60HZ so you can use a
mains-powered
clock for the display (using amplifier and transformer wired
"backwards").
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