On 12/30/2010 05:10 AM, Magnus Danielson wrote:
Fellow time-nuts,
I've modified my TADD-2:s by sniffing the input clock on pin 2 of the
PIC and wired it over to the output 6 signal selection pin header where
it goes further to the output polarity inverters and finally output.
This way I can use the input shaper of the TADD-2 and output driver to
improve my sine signals slew-rate.
The TADD-2 only generates 5 frequencies (it has two variants of 1 Hz, 1
Hz and PPS) so I thought I could use one of the outputs for this purpose.
First test-runs shows that I have now lowered my measurement floor at 1
s from 2,83E-11 to 1.05E-11. This could be improved on by removing some
unnecessary damping needed until I have DC-blockers in place.
I think the modification is encouraging as it stems from only adding a
wire and un-jumping a jumper.
My follow up analysis of this modification is that I've moved from being
WPM limited (white phase modulation) to become FPM (flicker phase
modulation) limited. As expected, the MDEV plot gave it away in clarity
while it could only be hinted in the ADEV plot.
I have not located the main source of flicker, but my suspicion lies
within the TADD-2 design. The input comparator is my most likely guess,
as there is a lovely 5 MHz sine slope for the flicker noise of the input
comparator to play with. Considering inserting a bypassed resistor in
series with R2 in order to lower the flicker noise of that amplifier.
Any comments?
Cheers,
Magnus
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