Am 07.01.2011 00:24, schrieb Magnus Danielson:
For a SERDES to be useable as a high frequency input, the Rx SERDES
needs to be able to use the reference clock as clock source rather
than doing clock recovery. While the SERDESes I have seen is able to
do that, one always want to check that detail before going further
into the design. For reference you typically use a SAW-oscillator
which in this case probably should have a VC input so you can lock it
up. Should not be too hard to find a suitable one.
On The SP605 board, you can inject the clock via 1 or 2 SMAs, single
ended or differential
I've considered this approach myself, but just not got around to cook
something up.
It's a bit of a design-challenge to do a parallel trigger detection
and event counter, but it is doable.
Yes.
If you look at the input signal as a 4 GB/s bit stream, you get it
served as a 16 or 32 bit wide stream
at 1/16 or 1/32 the rate. Recognizing the 0->1 and 1->0 transitions may
need some pipeline stages
and some work, but it is not really difficult.
The time stamp is simply the serial number of the 16/32 bit word and the
location of the bit that flips.
Plowing with the power of a thousand chicken.
Gerhard :-)
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