On 30/01/11 23:08, ehydra wrote:
I'm not sure if I overview the problem correctly. Hm, why not run the
cable back and measure the round time? Half this time und you know the
delay of one way. Then you can shift this with a PLL away.
A similar scheme is used in almost all modern PC clock distribution
chips. A bunch of PLLs on the chip. Severals are available. For example
Cypress Semi.
The LHC at Cern and associated accelerators build up cable distance.
They also have a myriad of different timing requirements. Essentially
they try to do away with them once and for all. I'm not convinced they
can do all of them in this round... but can't blame them for trying.
Only then they will learn the real requirements and problem areas.
Cheers,
Magnus
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