Hi Bert, Well, without the averaging I think I was correct (I was obviously not considering the averaging). Your implementation with averaging surely smooth this proportionally and yes you end up better than 0.0625 as more you integrate. Please consider then the numbers you may find relevant and the corresponding integration time. (that was not really the point in my email).
But since all topologies can average I presume you agree that potential differences between systems as remarked in my email still apply. Namely an offset at a frequency drift that is basic behavior of any FLL you wont have on a PLL. All that may fall below most practical needs(1), I agree... But in the timenuts spirit ought to be pointed out... right ? ;-) Luis Cupido ct1dmk. p.s. (1) folks running several Cesium stds don't be offended I'm not saying your needs are not practical :-) ;-) hi.... Bert, VE2ZAZ wrote:
Luis, You said: <<Furthermore the frequency counting resolution is 16 seconds, so the ZAZ gpsdo won't lock better than 0.0625Hz.>> On my GPSDO design, a single 16-second frequency sample does have a resolution of 0.0625Hz. But the FLL firmware does averaging over as many samples as you want before adjusting the OCXO. So I don't agree with your statement that the ZAZ gpsdo won't lock better than 0.0625Hz. In fact, I have never seen my design go worse than 1x10E-9. It usually sit below 5x10E-10. This concurs with the many reports I got from other users. Please elaborate. Thanks, Bert, VE2ZAZ
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