You're right, Max, I didn't think about subsampling for this - that
would give a more efficient implementation - no LPF, say two 74HC390s
to divide by 10,000, a 74HC74 with one half as a divide by two to get
to 20,000, the other half as the sampler/downconverter, and a
74HC4046A PLL. So, four common ICs to do the DSP/PLL portion.
Here's an example sampler application I just looked up, showing
appropriate connections:
* www.wseas.us/e-library/conferences/2005prague/papers/493-208.doc
Ed
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