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Holzworth's HX2410
<http://www.holzworth.com/Spec_sheets/HX2410_Web_Datasheet.pdf> claims
femtosecond jitter albeit with CMOS outputs.
This is difficult to achieve (especially at the lower end of its input
frequency range) with a comparator with 1ps of internal jitter.
A simple differential pair with the appropriate gain and bandwidth will
have somewhat lower jitter than a comparator, however as long as the
jitter is lower than that of the following logic achieving the lowest
possible output jitter from the sine to LVDS shaper may be somewhat
pointless.
Bruce
Bob Camp wrote:
Hi
With a 180 MHz sine wave, your dv/dt should be pretty fast (>= 1 V/ns). The
LVDS he's running into is likely slower than that (<= 0.6 V/ns).
My guess would be that bandpass might help for phase noise. It's not real
clear that a practical Collins style setup would add much.
More or less - if the input speed is already faster than the output logic,
is there actually a benefit?
Bob
-----Original Message-----
From: [email protected] [mailto:[email protected]] On
Behalf Of Bruce Griffiths
Sent: Friday, September 09, 2011 7:08 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Sine to LVDS
Javier Herrero wrote:
Hello all,
I think that the same question that has been discuted here a zillion
times but usually around 10MHz... anyway, what would be the best way
to convert a sine wave to a LVDS clock (preferably duty cycle 50%) at
180MHz?
Texas Instruments suggest a LVDS receiver as a comparator
http://www.ti.com/lit/an/slyt180/slyt180.pdf but time ago this was
discussed here, and not very favoured due to the high hysteresis of
the LVDS receivers.
Regards,
Javier
Use a true LVDS comparator (e.g. ADCMP604).
With 1:1 transformer coupled input and a pair of inverse parallel
schottky diodes across the inputs together with series resistors between
the transformer secondary to the comparator inputs should suffice for
inputs of +16dBm or more.
With sufficient input from a low noise source a cycle to cycle jitter of
1-2ps should be feasible.
Sub picosecond jitter is feasible if one cascades a series of low pass
filtered limiter stages.
Bruce
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