Sylvain Munaut wrote: > It's not generated from a DDS. It's from a xilinx PLD, then through an L and > then through a C to the RF connector. > The signal at the L output is fairly sinusoidal (at least monotonic near the > crossing), but after the cap, it's like that ...
While I'm waiting for my own FE-5680A to arrive... that "sine" wave certainly looks awful. What kind of signal is coming from the Xilinx PLD pin, before the L? Is it a simple 10 MHz square wave, or some kind of >> 10MHz PWM intended to approximate a 10 MHz sine wave? If it is a 10 MHz square wave, can I use that as a 10 MHz clock directly (probably through a digital buffer) or does it have a lot of jitter, which the LC filter was supposed to smooth out? _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
