Hal Murray wrote:
The TADD-3 uses 3 AC drivers in parallel, each going through a
51 ohm resistor.  Changing those resistors to 150 ohms should
work.  Maybe a bit lower to account for the impedance in the
drivers.  I'd probably check it with a scope.

[email protected] said:
That approach doesn't do anything for the Vcc and GND bounce exhibited  by
the driver chip. GND and Vcc bounce is the cause of the high frequency
ringing exhibited  by the TADD-3 outputs. This ringing can even be observed
at the outputs of inverters whose inputs are tied low or high in the same
package
I don't see how ground bounce is going to cause ringing.
Some load capacitance is required (even the capacitance of a short track on the board plus the output pin and output device capacitances will suffice) One of the ground bounce papers from TI will show the ringing due to ground bounce (eg http://www.ti.com/lit/an/szza038b/szza038b.pdf).
I'd expect the ringing to come from reflections from a long transmissions
line.
Transmission line current di/dt will interact with the supply (GND or Vcc) and output lead inductance.

Anybody know what the driver in a TBolt is like?  Here are 2 pictures looking
at the PPS from 2 TBolts.

This one has 10 ft of coax from one TBolt and and 25+10 ft from the other,
with no termination at the scope.
   http://www.megapathdsl.net/~hmurray/time-nuts/Rigol/ring-1.png

This one has 10 ft of coax with a terminator on one side and a 10X scope
probe right at the BNC on the other.
   http://www.megapathdsl.net/~hmurray/time-nuts/Rigol/ring-2.png


The output driver is a low impedance source possibly a 74AC04M (most likely candidate from the list of ICs used: http://www.prc68.com/I/ThunderBolt.shtml ).
Damping the crossover current induced transient in the supply leads
(bondwire and lead frame) inductance is one way to minimise this. A small
resistor in series with the Vcc pin often works well, the  resistor value
being chosen for near critical damping.
I'm not sure what you mean by crossover current.
During the output transition there is a short time interval (in a CMOS inverter stage) where both the n channel and p channel devices are both on causing a current to flow between Vcc and ground even with no external load.
I'd expect a "damping" resistor in the Vcc lead to slow down the rise time.
If you make it slow enough there won't be any ringing because the rise time
will be longer than the round trip time.  Then you can treat the transmission
line as a capacitor.
Thats certainly not the case in the FS730C, the risetime isnt appreciably affected by the small (4R7) damping resistor in series with Vcc. Adding a series damping resistor in series with the output is insufficient to suppress ringing.
I'd expect a resistor in the Vcc lead would not slow down the fall times.


If you want a slower rise time, you can also use HC rather than AC.  They
probably aren't strong enough to drive a 50 ohm terminator.

Using surface mount packages reduces the inductance.  (slightly?)

Another option is the bus driver chips that have multiple Vcc/GND pins.

GND bounce is still readily seen, the amplitude decreases somewhat but the associated ringing frequency for a given load increases.
Another problem with the TADD-3 is the sharing of a driver chip by
different input frequencies which leads to intermodulation between the 2
outputs.
Yup.  Job security for designers.  :)

If you read the fine print in the data sheets for high speed chips, they
usually specify a marketing number with only one output changing.  The good
data sheets tell you how much it slows down when multiple outputs change.


Its not quite that simple transients are observed on quiet outputs due to output transitions on the switching outputs. If transitions occur simultaneously on 2 different frequency inputs connected to the same chip then simultaneous switching effects modulate the effective propagation delay of the output transitions. e.g. a 1MHz output may exhibit phase modulation at 100KHz if the 1MHz and 100KHz signals share the same output driver chip.

Bruce

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