[email protected] said: > BTW: does anyone know how these days low cost FPGAs perform in terms of > jitter? (the data sheets are kind of scarce in that regard). And how do they > compare to state of the art ECL logic?
Generally, not good. The general problem is that they have a lot of logic and a lot of I/O drivers and shared power/ground pins. Things are messy if you have multiple clocks. Things are better if you only have one clock and better if you don't have any nearby drivers switching at the same time. For a few critical signals, you could reclock in an external FF. -- These are my opinions, not necessarily my employer's. I hate spam. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
