Digging through the literature online, I see the high voltage LDOs are
still PNP, at least for the manufacturers that show representative
circuits. I was pretty such of this when you did your post, mostly
because I couldn't see how you would drive the NPN and maintain a low
dropout. [You would need circuitry to drive the base that would have to
function a VBE above dropout.] If low droput wasn't required, then by
all means, I'd design with a NPN pass device to avoid the saturation
killer circuit.
Some random TI parts:
http://www.ti.com/lit/ds/symlink/lm9076.pdf
About 30 to 40db rejection at switcher frequencies.
http://www.ti.com/lit/ds/symlink/lm2931-n.pdf
About 55 to 70dB rejection at switcher frequencies.
Note the rejection graphs are a bit misleading since they are measured
with sine inputs, while the switcher noise has plenty of harmonics.
When I build a project for myself, I always use the P-fet based LDOs.
Usually TI designs, though I never worked for them, so I have no inside
knowledge of their design. They test fine. I just know it is
substantially easier to design a LDO with a P-fet in terms of stability,
simply because there is one feedback path, and MOS modeling is better
than bipolar.
Some of the worst LDOs I've come across are from Micrel. I can't imagine
how that company stays in business. [Look at their financials and the
market agrees with me.] TI, LTC, Maxim, generally good stuff, though you
can usually find a stinker device if you look hard enough. Something
like a LDO is usually a solo project so it depends a lot on the designer.
Surprisingly, the wiki is pretty decent for LDOs, paying homage to Bob
Dobkin.
http://en.wikipedia.org/wiki/Low-dropout_regulator
On 2/27/2012 2:46 AM, [email protected] wrote:
Those were bicmos designs where the LDO was to provide voltage for running
controller chips.
I've only done PMOS for stand alone LDO.
-----Original Message-----
From: Steve<[email protected]>
Sender: [email protected]
Date: Sun, 26 Feb 2012 23:54:20
To:<[email protected]>
Reply-To: Discussion of precise time and frequency measurement
<[email protected]>
Subject: Re: [time-nuts] Power Supply Noise Affects Thunderbolt 1 PPS
Having designed LDO chips, people expect them to perform miracles
well beyond reality. If you have a PNP pass and you are sitting near
dropout, you get control loops that are an ugly combination of a path
to keep the PNP from getting saturated plus one to control the
voltage.
I never really warmed up to
PNP pass devices, but they are best for high voltage applications.
I was under the impression that the industry as a whole got away from
PNP pass back in the 80s. Off the top, I can't think of any PNP pass
regulation designs worth using.
You've got my curiosity when you mentioned high voltage. Seems to me
that PNP is even worse at high voltage, owing to the majority holes as
carriers rather than majority electrons as in NPN.
Why are PNP better for high voltage than NPN? (I've been using PNP for
nearly everything for about 20 years) .. every now and then i get lazy
and grab a PNP, but that's beyond the context ;)
Steve
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