In message <Pine.LNX.4.64.1203142345310.2459@tesla>, Marek Peca writes:
>I will share my few bits of worked experience. But it may seem obvious.
>
>> I'd say to go "100% SDR". In other words a simple front and that
>> pushes as much of the functionality into software as possible. The
>> carrier is only 60K. That is low enough that one can directly
>> digitize the RF using an ADC that samples at only 192K/sec.
>
>Not necesarilly. I received 77.5kHz very well in first sampling mirror,
>sampling using ADS7813 16bit ADC @44ksps, yielding carrier at 10.5kHz in
>discrete-time domain.
Here's a really interesting platform for VLF SDR work:
http://www.seeedstudio.com/depot/dso-nano-v2-p-681.html?cPath=174
1MSPS 12 bit ADC, input amplifier/attenuator, display, USB interface,
and rechargeable lithium battery.
For $89...
Too bad it doesn't have a 10MHz reference clock input for time-nuttery.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
[email protected] | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
_______________________________________________
time-nuts mailing list -- [email protected]
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
