I have been looking at CPLD and FPGA designs for aggregating the logic required but keep running up against their lack of jitter specifications for asynchronous applications. Is the part and development cost worth replacing a handful of discrete logic when the CPLD or FPGA is dedicated to such a small function?
I figured I would just have to try a couple of designs and measure how well they do. On Fri, 27 Apr 2012 10:54:57 -0400 (EDT), [email protected] wrote: >The Altera Max 3000A as I mentioned before will do all TTL devices, it has >an extensive library easy to use and very cheap. All That at 200 MHz. I >became a believer and others I introduced to it love it to. In an hour from >downloading the free software you can have your first design. If I can do it >every body can do it. >Bert Kehren > > >In a message dated 4/27/2012 9:53:16 A.M. Eastern Daylight Time, >[email protected] writes: > >On Wed, 25 Apr 2012 19:17:43 -0300 >Daniel Mendes <[email protected]> wrote: > >> About replacing the 74ACT175... there´s a company called "Potato Semi" >> (well.. they make "chips", right?) whose sole business is to make damn >> fast 74 logic. Their chips can be bought at ebay in small quantities. >> Look at this 600MHz D flip flop: >> >> http://www.potatosemi.com/potatosemiweb/datasheet/PO74G74A.pdf > >Hmm... looks interesting. Though, i probably would take >standard ECL instead of those because of higher availability >(you can get them from mouser, digikey & co). > >But good to know that at least someone is still trying to improve >standard 74xx devices, for all those who do not want to use an CPLD/FPGA. > > >Attila Kinali _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
