Michael Tharp wrote:
On 05/27/2012 06:23 PM, Bruce Griffiths wrote:
The principal problem with conventional DDS implementations is phase
truncation spurs which can occur close to the desired carrier.
Virtually all commercial DDS chips produce such phase truncation spurs.
It is possible to eliminate such spurs if one implements a custom DDS
using an FPGA and an external DAC.
In this case the performance is limited by the DAC.
How specifically does the FPGA resolve the problem? I have a FPGA
already for the phase comparator, it's just a "simple" matter of
figuring out how big of a DAC to get and what data to feed it...
By implementing a design thats phase truncation spur free like:
/Ultra low Phase noise DDS/ , Fred Harris, Chris Dick, Richard Jekel in
Proceedings of SDR06 Technical conference and Product exposition.
Both amplitude and phase errors arise due to phase truncation and its
essential to correct both.
rather than the simplistic technique used in AD (and other) DDS chips
where the phase and amplitude errors due to truncation remain uncorrected.
Another approach is to use a cascaded mix and divide technique
<http://www.karlquist.com/FCS95.pdf> to restrict the effective tuning
range of the DDS.
The amplitude of DDS generated spurs is thereby significantly reduced.
Great paper, this looks like it could be interesting as a standalone
filter. It's just a little over my head (self-taught digital guy) but
since I don't need to hit a home run on the first try, I'll keep it in
mind.
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