On 06/05/2012 03:31 PM, Attila Kinali wrote:
* The XC6SLX9 is<10USD more expensive than the SLX6. I think the added value of having twice as much "real estate" would justify the additional price.
Some vendors don't even stock the SLX6, including Digi-Key! Agreed though, it would be neat if a CPU capable of doing fixes could be fit onto the FPGA alongside. Might be impractical though, a DSP would probably be more appropriate. Still, from what I can tell a FPGA makes a decent PPS-level phase comparator. You can even gang them up with a phase-shifted clock to get finer resolution.
* Connect the enable pin of the OSC1 to a 2-pin header, so it can be disabled with a simple jumper. And put a SMA connector into the path between OSC1 and the LMK03806 (probably not mounted by default) in order to make using an external clock source easier. I assume that you are running the ADCs in multiplexed mode and the FPGA at 128MHz clock? How about design tools for the FPGA? As far as i can tell, the ISE WebPack does not support the Spartan 6 family.
WebPack does support XC6, or at least the mid-range parts and below. I have a XC6SLX45 dev board and have no problems generating bitstreams.
-- m. tharp _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
