And try to put the unused I/O pins to GND too. Xilinx suggests, to reduce noise, to ground the FPGA using as more free I/O pins as possible and configure them as low logic level. Of course this trick does apply to other brands too.
On Sat, Jun 9, 2012 at 6:54 AM, Hal Murray <[email protected]> wrote: > > * Connect all free pins of the FPGA to a 2.54mm header pin connector > > Don't go overboard on the "all" if that makes a mess of the routing or > layout. > > Be sure to put "enough" ground pins on the header(s). Power too. > > > -- > These are my opinions. I hate spam. > > > > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
