It is very simple: let me describe it first. Two dividers and an XOR gate. This is an FLL and only the frequency consistency is guaranteed but in this case is enough. The advantage is that only a CPLD is used. I'll send the VHDL so that it will be possible to use any CPLD. It is possible to implement a real PLL but in my version an external OP-AMP is needed as I prefer the UP/DOWN output to be combined externally .
On Fri, Jul 6, 2012 at 9:05 PM, Bill Dailey <docdai...@gmail.com> wrote: > What if I post a schematic with a Lattice M4-64/32 CPLD? If you can program > this CPLD I can send the .JED file, the schematic... > > --------------------------------- > > I could probably get that done... would have to get a board made... never > done it but could probably manage...some kind of usb blaster to program > it. I presume the .jed is the code? I can solder for sure. Would I be > able to look at the code so I can learn something? > > -- > Doc > > Bill Dailey > KXØO > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
