On 7/22/2012 2:41 PM, Bob Camp wrote:
Hi
The feedback inverter is indeed a problem with fast logic, just bias it to mid
point off the supply instead.
1. Do not use CMOS inverters. Even though so much has been published on
using these in linear mode by
adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC,
etc) have so much high frequency gain they are
likely to take off into oscillation on their own.
YMMV, but in the 5071A cesium standard I designed
in a 74AC00 biased at half the supply voltage to
make an 80 MHz clock from a sine wave. We never
observed oscillations. The feedback resistor method
may be optimum for getting the gate at the exact
center of its range which might encourage oscillation.
We did not have a requirement that the gate is stable
with no input, like it might need to be if it were
a front panel input on an instrument.
Rick
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