On Wed, 22 Aug 2012 19:00:10 -0700, Hal Murray <[email protected]> wrote:
>[email protected] said: >> The amount of jitter verses logic family is all over the place as well. Take >> a look at an LS verses an HCT vs an S family and you will see what I mean. >> Some of them are very nasty, and are not all created equally. > >Is there any collection of hard data? How much does it depend upon >manufacturer or test setup? How much couples through from power supply? I have not seen any. The jitter varies not only between logic families but also between manufacturers and IC processes. It is usually unimportant for logic intended for synchronous applications. The circuit design itself can be critical. If you want to avoid testing and qualifying parts, then some of the faster logic families have guaranteed jitter specifications. They also tend to include switching threshold control or compensation to increase power supply rejection. >Does the jitter scale with prop-time? Usually but not always. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
