In message <[email protected]>, Dennis Ferguson wr ites:
>If you >are using a PLL in both cases, however, then the problems are >essentially the same. Well, not quite: Depending on the stiffness of your PLL, you can minimize phase error at the cost of frequency error or frequency error at the cost of phase error, and either is a valid engineering decision depending which of the two are more important to you. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 [email protected] | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
