To Paul re my receiver thoughts.
You are absolutely correct in some regards and for some
implementations.
The limiter must have very high dynamic range and must not convert
changes in input level to
changes in transmission phase; i.e. No AM to PM conversions. Thus my
specific suggestion of the
Analog Devices parts. Normal diode limiters and such simple stuff won't
work.The internal configuration
of Low AM-PM limiters is 9 or 10 stage of emitter coupled differential
pairs. Now conveniently available as ICs.
Likewise you need a slow PLL in front of the divide by 2 in order to
coast through fast fades. Alternatively you can use the log output of
the limiter as an instantaneous level indication and not sample the
input during periods of no signal. Some implementations could use a
really stable frequency standard as the VCXO in the PLL and freeze the
control voltage during fades. I did this once with good success. Using
the HP 10544 we could ride through a 2 hour outage and maintain code
synchronization. So it is possible.
With regard to filter phase, I mentioned BW because it is easier to
measure. Wider BW = better phase response for all else being equal.
However properly implemented - the suggested configuration should work
OK. Once upon a time -1976 -
A similar setup was used to extract the carrier for a BPSK demodulator
from a spread spectrum IF signal.
Good luck with your design.
-73 john k6iql
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