If you daisy chain the cable (or PCB trace) past several receivers, the signal at the non-terminal receivers will have a flat spot in the middle. It will go up half way, stay there for the time for the signal to get to the end and back, then go to full voltage. That flat spot is asking for troubles. Noise may cause multiple clock edges. =====
Depends on how far apart your end of line loads are. If they are within a rise time (length) of the end of the line it is not a problem. For TTL etc with 1 ns rise time that means a foot. Be conservative and say 6 inches. But with SMT parts that is a fairly generous standard. Especially given the fact that the loads (AC, HC, LVC, etc) are capacitive and draw no current (except on transitions). That will slow the rise time. But as Hal points out, ECL is different. With rise times on the order of .1 nS your end of line unterminated loads must be within an inch of each other. A good ECL manual (the old Motorola ones were very good) will keep you out of trouble. They also go into stripline and microstip design. Very handy. Think of it: we live in an age when 1nS is considered slow. And the design rules at that speed are generous. There is a lot of fun to be had if you are moderately careful. Or a LOT of bench time if you are not. Engineering is the art of making what you want from what you can get at a profit. ------------------------------ > > >Message: 6 >Date: Mon, 26 Nov 2012 13:11:13 -0800 >From: Hal Murray <hmur...@megapathdsl.net> >To: Discussion of precise time and frequency measurement > <time-nuts@febo.com> >Subject: Re: [time-nuts] pulse height >Message-ID: > <20121126211113.94386800...@ip-64-139-1-69.sjc.megapath.net> >Content-Type: text/plain; charset=us-ascii > > >saidj...@aol.com said: >> Nice page, but your first plot with R1 = 0 ohms and no R2 shows too much >> ringing. > >It shows what I expect. I thought it was an example of what happens if you >set things up that way, not how to get the best results. > > >> With proper impedance matching that setup will give the best results, >> meaning the highest voltage pulse, no ringing, the lowest power consumption, >> etc. > >"proper impedance matching" isn't a well defined term. > >I'm familiar with 2 approaches. The one I think you are referring to is >generally called "series termination". This is Didier's R2=infinity and >R1=line. > >You place a resistor between the source of the signal and the transmission >line. That resistance (correcting for internal resistance in the source) >matches the transmission line impedance. At the start of the pulse, the >source resistance and the transmission line impedance make a simple voltage >divider. The pulse on the line will be half the driving voltage. When the >pulse gets to the far end (no termination), it reflects back. That doubles >the voltage. A scope (or chip) at the far end sees a clean transition from 0 >to full voltage. When the reflection gets back to the source, the source >rises to full voltage and due to the termination there are no more >reflections. > >One advantage of source termination is that it doesn't use any power except >when switching. > >One disadvantage is that only the far end sees a clean signal. If you daisy >chain the cable (or PCB trace) past several receivers, the signal at the >non-terminal receivers will have a flat spot in the middle. It will go up >half way, stay there for the time for the signal to get to the end and back, >then go to full voltage. That flat spot is asking for troubles. Noise may >cause multiple clock edges. > > >The other approach is to drive the line with a low impedance and put a >terminator at the far end. I don't know of a good term for this. This is >what I think of when I hear an unqualified "termination". In a discussion >like this, I would probably call it "far end termination". It's Didiers >R1=0, R2=line. The signal starts at full voltage, goes down the line at full >voltage. The far end sees a clean transition from 0 to full voltage. There >are no reflections. > >The voltage actually depends on the internal impedance of the source. >Sometimes you set the source impedance to match the line. That gives half >voltage, but absorbs any reflections due to manufacturing tolerances or >whatever and provides short circuit protection. > >This approach eats power but works with multiple receivers. It's common in >lab gear and used with ECL logic. > > > >-- >These are my opinions. I hate spam. > > > > > > >------------------------------ > >_______________________________________________ >time-nuts mailing list >time-nuts@febo.com >https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > >End of time-nuts Digest, Vol 100, Issue 116 >******************************************* > > > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
