Hi I believe you will find that NPO's are your best bet by far for short delays.
The R's and C's on a simple semi are going to have some pretty major tempco's. If they go with a fancy process they can change that. Normally to keep things cheap they use the simple process. Bob On Dec 17, 2012, at 2:55 PM, David <[email protected]> wrote: > You would not want to do this for long delays obviously. A digital > counter with the delay used as a vernier would be more appropriate > there. That gets complicated fast if the input is asynchronous. > > Analog first order compensation of the temperature coefficient is > straightforward using the same techniques that are used for voltage to > frequency converters. Unfortunately, polystyrene capacitors are no > longer produced. Digital calibration might be easier to design and > would be a good idea for verification of performance anyway. > > I wonder what the temperature coefficient is of the Maxim's > programmable delay lines. I do not see it in their datasheets. The > On semiconductor one I checked is greater than 1000ppm/C but its > maximum delay is 12.5 nanoseconds. > > On Mon, 17 Dec 2012 14:04:54 -0500, Bob Camp <[email protected]> wrote: > >> Hi >> >> With R-C delay generators, temperature coefficient is likely to be an issue. >> NPO will get you to 30 ppm/C. Most resistors will be up in the 50 or so ppm >> / C range. On top of that you have the contributions of what ever strays >> might be running around. >> >> If you are trying to set up say a 1 us delay, you will get ~ 50 ps per >> degree C in your delay. That's a lot ..... >> >> Bob >> >> On Dec 17, 2012, at 1:56 PM, David <[email protected]> wrote: >> >>> On Mon, 17 Dec 2012 10:19:43 -0800, Hal Murray >>> <[email protected]> wrote: >>> >>>> >>>>> A fifth solution is to use a pulse delay generator like a DG535. I use >>>>> this >>>>> to create high-resolution early/late 1PPS sync pulses. They show up on >>>>> eBay, >>>>> but aren't cheap. For bargains, watch for older model programmable pulse >>>>> delay generators by BNC (Berkeley Nucleonics Corporation). >>>> >>>> Thanks. Those are more $$$ than I'm interested in right now, but might be >>>> a >>>> useful tool sometime in the future. >>>> >>>> Another approach is to use a scope: trigger on one PPS and adjust the >>>> delay >>>> (which might be negative) and sweep speed so you can see the other PPS >>>> signal. Maybe I'll play with this to see what sort of results I can get. >>>> >>>> >>>>> Lastly, there are cute little delay boxes (www.ebay.com/itm/150962422699) >>>>> that might work. Not sure how stable they are at the ns level. But it >>>>> would >>>>> be fun to measure. If someone opens one of these please tell us if it's a >>>>> coil of wire, some kind of LRC filter delay, or if they use those Dallas >>>>> delay chips. Which is another solution for you -- google or eBay search >>>>> for: >>>>> silicon delay line. >>>> >>>> You can make a reasonable delay line by using the lumped circuit >>>> approximation for the L and C for the appropriate impedance transmission >>>> line. I assume that's what's in the delay boxes. I should try that >>>> sometime. Thanks for the reminder. >>>> >>>> The delay chips I've looked at before used gate delays. I think they were >>>> Motorola rather than Dallas. I just poked at a few Maxim data sheets. I >>>> didn't find out how they implemented the delays. >>>> >>>> I think some of the clock recovery chips tune delays by tweaking the >>>> threshold voltage. >>> >>> I have been testing just using adjustable RC delays into a logic gate >>> to generate pretrigger pulses for sampling oscilloscopes. Accuracy >>> depends on a complete reset of the capacitor and tracking between the >>> RC charge voltage and gate threshold voltage. Worst cast jitter for >>> TTL has been in the 100s of picoseconds range because of supply >>> voltage sensitivity. Different families of TTL and CMOS logic all >>> performed about the same. >>> >>> Here is the jitter measurement that came from the RC logic gate delay >>> test: >>> >>> http://www.banishedsouls.org/c2df3757f1/PG506/PDJ%20lolcat.jpg >>> >>> Much better is to use a differential comparator or differential input >>> ECL which solves the threshold variation errors and a fast (it really >>> isn't all that fast) ramp generator with a precision reset. The >>> differential input allows the ramp rate and threshold voltage to be >>> linked allowing ratiometric operation to reject power supply or >>> reference voltage variation and noise. >>> >>> My next pretrigger generator is going the differential comparator or >>> differential ECL route with a fast ramp and precision reset. I expect >>> jitter to be significantly better than 10s of picoseconds for delays >>> up to about 100 nanoseconds. If I get down to 10 picoseconds of >>> jitter, I will be happy since I have no real way to measure much below >>> that. >>> >>> _______________________________________________ >>> time-nuts mailing list -- [email protected] >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >>> and follow the instructions there. >> >> >> _______________________________________________ >> time-nuts mailing list -- [email protected] >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
