Hi Fabio taking BJTs deep into saturation stores a lot of charge in the
collector base capacitance. this must br discharged before a state change
can occur. LSTTL gets round this and gets the speed at lower currents by
clamping the collector to only just in saturation with a schottky diode
between base and collector. Higher speeds are obtained with a long-tail pair
like configuration, which switches (diverts) the current flow between left
and right transistors for the two logic states. The current and power
dissipation is high but speeds 10 times saturated logic are obtainable. see
ECL, MECL, or PECL logic family schematics.
Alan
G3NYK
----- Original Message -----
From: "Fabio Eboli" <fabi...@quipo.it>
To: "Discussion of precise time and frequency measurement"
<time-nuts@febo.com>
Sent: Saturday, December 22, 2012 11:00 PM
Subject: Re: [time-nuts] Questions about TAC frontend, and some measurements
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
Buffering the ramp with an opamp requires that the opamp settling
time be known so that the opamp has fully settled before a sample is
taken. With a charge redistribution ADC that has a sampling switch
connected to a capacitor array a buffer isnt usually necessary.
Bruce
I was planning to read the voltage with a microcontroller's ADC.
I will set a fixed delay from the PPS rising edge and start
sampling there. To do so I need that the voltage on integrating
capacitor to stay reasonably stable during the delay.
Fabio
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