Epic fail:
"Not fancy SPICE simulations."

Note there are many situations where you force the result (if you call 
hysteresis a biased scheme) simply because to do otherwise is a more serious 
problem.

-----Original Message-----
From: Azelio Boriani <[email protected]>
Sender: [email protected]
Date: Mon, 25 Mar 2013 14:09:54 
To: Discussion of precise time and frequency measurement<[email protected]>
Reply-To: Discussion of precise time and frequency measurement
        <[email protected]>
Subject: [time-nuts] About metastability

Thomas Cheney, October 1979:

"In closing, there is a great deal of theoretical and experimental
evidence that a region of anomalous behavior exists for every device
that has two stable states. The maturity of this topic is now such that
papers making contrary claims without theoretical or experimental support
should not be accepted for publication."


Philip Freidin 8/27/2003:

"Nothing improves the MTBF of a metastable synchronizer better than
just waiting longer. Not clocking the intermediate signal on the
negative clock edge. Not voting. Not threshold testing. Not adding
noise. Not fancy SPICE simulations. Not predicting circuits. Not
circuits designed to bias the outcome to either 1 or 0. Not
clocking it twice as fast through twice as many flip flops.
Nothing."
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