Minimum clock width is not the window for metastability. That is
usually 10s to 100s of picoseconds.
On 3/25/13 3:20 PM, Attila Kinali wrote:
On Mon, 25 Mar 2013 11:18:06 -0700
Chris Albertson <[email protected]> wrote:
Ie the output of the counter becomes
(more or less) random. Which in turn means the lower 4 bit of the
input to the PI control loop are wrong[1]. Or in terms of time, we
might be off by +/-2^4*42ns=672ns, which is a major hit against the
PI loop (like knocking it with a sledge hammer).
But these numbers don't go directly to the PI loop, there is a
software layer between that can inspect for outliers.
The problem here is that these outliers need not be a seldom occurence.
If you take a LEA6-T as PPS source, you get the PPS pulse within +/-10ns
in 90% of the cases. The 24MHz clock is, even though it's a cheap
crystal, still a crystal. So you can assume a stability of better than
10^-7 short term (couple of seconds to a few minutes), probably in the
range of 10^-8 to 10^-9.
The window for metastability is 15ns (minimum clock pulse width).
Now we have two things to consider:
1) Both the clock and the PPS are relatively stable compared to
the "size" of the 15ns. Ie if we ever get into region of metastability,
the probability that one of the next PPS will trigger again a metastable
condition is relatively high.
2) We have a 24MHz clock, which means the clock pulse width is
20ns (T=1/24MHz, T/2 = 20ns). Ie the probability that our clock pulse
is too short is 75% (15ns/20ns).
I dont know why this isnt a big issue with the Shera GPSDO.
I guess that the specs of the 74HC4520 are very conservative
an that the minimum clock pulse length is rather in the range
of 5ns than 15ns for most devices and operation temperatures.
It might also be that the probability of bits being affected
is less for the upper bits than for the lower bits.
Or the PI loop is stable enough to deal with the additional noise.
Attila Kinali
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