Javier Serrano wrote:
On Tue, Jun 25, 2013 at 4:36 AM, ed breya<[email protected]> wrote:
4. It seems to me that whenever fd is much higher than fc (fd>>fc), that
fd could be used instead to trigger the second DFF, which would reduce the
metastability of the first DFF somewhat, and also synchronize the output
signal closer to the edges of fd - but with some metastability from that
too.
Clocking the two FFs of a synchronizer with different clock signals will
not work against metastability. When the edges of fd and fc are very close
in time, there is a slight chance that the output of the first FF will be
in a metastable state for some time. By clocking the second FF with fc you
allow for a full (guaranteed) period of fc for that output to stabilize to
a solid '0' or '1'. If you clock the two FFs with two different clock
signals you don't have that guarantee. There should be a big gain to be had
somewhere else to do something like that, but I can't see it. I must say
all my experience is with fc very close to fd in frequency, so maybe I am
missing something about the fd>>fc case.
Cheers,
Javier
US patent 6441601 describes using a D flipflop as a phase detector when
fc>fd.
Fd ~ 13.4Mhz, Fc ~ 10.23MHz
In this case the samples are permuted to achieve the right order of
phase differences.
I have clocked a 74HC164 with a 5.000055MHz fc whilst the D input is
driven at 10.000 MHz to produce a 110 Hz " beat note".
Bruce
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