Hi Flip flops are sampling devices. All samplers can / do act as mixers between the clock (sampling) frequency and the input (data) frequency. That's all that's going on. Look at it like a mixer and it all makes sense.
Bob On Jun 24, 2013, at 8:13 PM, ed breya <[email protected]> wrote: > I am revisiting that tracking generator reference I brought up here a while > back, and trying to get my head around how a DFF can take the difference > between two frequencies. I have studied and thought about the various > topologies and conditions, and searched online for good explanations, but > haven't found anything concise that applies to this simple case. During the > last discussion on this matter, I learned that another DFF should follow the > first, and be clocked the same, in order to reduce effects of metastability. > For the actual application, I believe there are limits to the differencing > process, so I'd like to check here to see if my thinking is right. > > First, let's call fd the frequency of the D-input, and fc the clock, which > produce a signal fo at the Q output of the first DFF. > > 1. It seems to me that whenever fd and fc are within a factor of two of each > other, either one can be viewed as sampling the other below the Nyquist rate, > so an alias signal fo, the difference frequency, is produced. It doesn't > matter which input frequency is higher. > > 2. It seems to me that whenever fc is much higher than fd (fc>>fd), then it's > clearly sampling above Nyquist frequency, so no aliasing occurs - just a > delayed (by a fraction of a cycle of fc) version of fd shows up at the Q > output, and fo=fd. If so, then this should be true all the way down to > fc>2*fd. > > 3. It seems to me that whenever fd is much higher than fc (fd>>fc), then it's > clearly undersampling, so aliasing will occur, producing fo=fd-n*fc, where n > is the highest integer that allows fd>n*fc. If so, then this should be true > all the way down to fd>2*fc. For example, if fc is 200 kHz, and fd is > 15.8833333 MHz, then n=79, and fo=83.3333 kHz. 79*0.2=15.8 MHz, so > 15.883333-15.8=.08333 MHz. If fc=5 MHz, then n=3, and fo=883.3333 kHz. If > fc=4 MHz, then n=3, and fo=3.883333 MHz. > > Now onto the second DFF, which reduces the metastability effects of the > first. Let's say that normally the Q output of the first goes to the D input > of the second, the clocks of both are the same fc, and the Q output of the > second is the "cleaned up" version of fo, delayed by a fraction of a cycle of > fc. > > 4. It seems to me that whenever fd is much higher than fc (fd>>fc), that fd > could be used instead to trigger the second DFF, which would reduce the > metastability of the first DFF somewhat, and also synchronize the output > signal closer to the edges of fd - but with some metastability from that too. > > 5. It seems to me that the fastest possible logic family should be used for > minimum metastability, even if slower ones can clock easily at fc and fd. So, > I'd prefer 74AC-type parts over HC, even at 15 MHz. > > So, do I get it, or am I missing something? Please be nice. > > Ed > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
