On Tue, Jul 2, 2013 at 12:32 AM, mike cook <[email protected]> wrote:
> > ... In most modern x86 CPU's you have a TSC which is a 64bit counter > incremented at the cpu clock cycle speed . You can capture that with a > single instruction. NTP uses that if it is available. So to get an > accurate TI you just take 2 samples and subtract. You just need to take > into account interrupt handling latency. I don't think this is available in > ARM under that name, but there is a cycle count register CCNT which does > the same thing. I think it is 64 bit as well. It is a nanosecond counter that runs off the system clock. However the "tick" normally is more then a few nanoseconds and from what I've seen is microseconds. I have looked at many samples over hours long periods and they were all even used apart. That said, for NTP it is more than good enough or shout I say at least 10X better than required. For a hobby type problem where the goal is just to see how well you can do even if there is no need then I think yo want a hardware implementation. Run a counter at 1GHz and have the leding edge of the PPS sample the counter. Net you need to modify the OS to use this counter for timing. You could build this or, there are some CPUs that have this already implemented. But in any case sampleing the Intel timer gets you to a few Usec and is more then enough for NTP. The leak like is the Ethernet connections which gives millisecond level performance no matter how good the server is. -- Chris Albertson Redondo Beach, California _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
