Hi Wolfgang, On 11/30/2013 10:32 AM, Wolfgang Wallner wrote: > Hello, > > thanks a lot for all your feedback (also in the other threads)! > It will take some time to read reed through all your recommendations :) > > On 11/28/2013 08:18 PM, Attila Kinali wrote: >> On Thu, 28 Nov 2013 10:35:33 +0100 >> Wolfgang Wallner <[email protected]> wrote: >> >>> I'm interested in the simulation of oscillator noise (especially in >>> discrete event simulators). >>> I came across this topic as part of the literature research for my master's >>> thesis, and have to admit that I really underestimated how complex this >>> topic is. >> Hehe. Join the club. But treat carefully, this can become quite addictive ;-) >> >> Can you explain what you are exactly doing? You talk about noise, but >> only mention allan deviation. ADEV is the right tool to measure stability, >> but not so much phase noise. > The interest comes from IEEE 1588, which is an interesting standard, but > the equipment is quite expensive (a single switch with transparent clock > support for >1000$). > This means it is hard to estimated what could be achieved with 1588, as > it is rather impossible to just buy some devices and try it out. > Questions which would be interesting are things like: > > *) what synchronization interval is need to achieve a specific > precision, and where are the limits > *) how does a long daisy chain behave (with/without syntonization in > each hop) > *) what happens when a link breaks and comes up some time later (how far > will the parts drift away) > > At my institute (TU Vienna, Computer Engineering) there has been a > bachelor thesis which dealt with simulation of IEEE 1588 in OMNeT++ (a > discrete event simulator). > But the assumptions where rather simple (both of the clock model and the > implemented version of IEEE 1588). > > For my master thesis I would like to enhance both aspects. > I would like to do a full implementation of IEEE 1588 and to use a more > realistic clock model. > > Implementing IEEE 1588 is rather straight forward. The standard is easy > to read, and it is not rocket science to implement this it in C++. > > But as already stated in my first message, I underestimated how hard it > would be to get a realistic clock model. It's a difficult topic because:
1) There is no defined clock model defined in IEEE 1588, so there is no way to generally specify what a 1588 device will do. I've checked this with one of the core 1588 guys and he agrees. 2) There is no defined network jitter model. You need to consider if equipment is 1588 aware or not, and it may be traffic load dependent, and there is a wide range of behaviors which does not fit "normal" noises. For 1588 aware switches and routers which works well, a first degree damping can be expected, but it is not perfect. The systematic behavior to low-frequency "noise" will leak through. The best you can do is build a few fair models and test with a few different noise-characteristics and see what they will do. Remember that it is not just the noise sources of your oscillator, you have systematic effects to care about, such as aging, initial frequency offset, initial phase offset, temperature dependence, PLL parameters etc. etc. Cheers, Magnus _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
