R2 is dominated by the adc sample switch on resistance and thus has a
relatively high tempco (~4000ppm/C).
C2 has a relatively low tempco (~100ppm/C or so)
To reduce the effect of the sample switch on resistance tempco on the
gain tempco of the TIC R1 C1 need to be proportioned so that R2 has
little effect on the gain temcpo.
R1 = 470 ohm, C1 = 1nF (NPO) appears to be about right for a 2.5MHz
synchroniser clock and the PIC you intend to use.
This should reduce the effect of the sample switch on resistance tempco
by a factor of 10 or more.
The minimum value of R1 is governed by the output resistance of the
tristate buffer and its tempco.
Bruce
Bob Stewart wrote:
Hi Bruce,
What are the tradeoffs with using different values for R1? I have no practical
experience at this, so all I can do is rely on the models. Does the fact that
R2 is in the PIC, and C1 is so tiny, make the value of R1 of less importance?
On my PIC, they list C1 as 5pf, R2 as effectively about 7K, and C2 120pf.
Bob
________________________________
From: Bruce Griffiths<[email protected]>
To: Discussion of precise time and frequency measurement<[email protected]>
Sent: Tuesday, February 18, 2014 9:35 PM
Subject: Re: [time-nuts] TIC model
The attached circuit schematic illustrates how this might be implemented.
Faster logic devices can be substituted.
R2, C2 approximate the equivalent input circuit of the ADC.
R2, C2 values will vary for each ADC.
The Shift register which acts as a synchroniser and produces various trigger
signals is clocked at 10MHz (assumed to be the uP instruction cycle clock rate)
The RC network charge time varies between 1 and 2 shift register clock periods
( ie a charge time from 100ns to 200ns).
Sampling a time stamp counter clocked at the same frequency as the shift
register is only required if the GPSDO local oscillator has a potential initial
offset of 100ppb or more.
If missing PPS detection is required then a PPS time stamp counter with a range
of several seconds is desirable.
Bruce
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