There are two ways that both positive and negative slopes could be used,
that is, with the input clocks and/or with the reference clock.
The PRU on the BBB is not really fast enough to identify the edge
direction at a 10mhz rate, so I only collect state changes in real time
and then sort it out the direction on the ARM processor afterwards. All
transitions are useful for glitch identification, and this does mean I'm
already capturing the negative edge of the input signals for free.
Admittedly, I'm not doing anything with this data as I currently filter
for rising edges fairly early on, but it is 'just a software problem' to
utilise data that is already there. _How_ to use the data is the point
of discussion, but it will be fairly trivial to implement any ideas and
see if they stack up in practice against real data.
Regarding the reference clock, utilising the negative edge could be used
to double the sample rate (like DDR RAM). I've already been using a
74AC14 Schmitt inverter on the reference clock, primarily as a buffer to
distribute the clock to each sampler (flip flop or shift register) and
the BBB, but also to try different sample timings (e.g. clocking the
samplers on the +ve edge and the BBB capture on the -ve edge for
example). Clocking different samplers on alternate edges (but with the
same input signal) is therefore relatively straightforward, and feeding
more sampling channels to the BBB is not too much of a big deal either.
It is not something I have tried though.
My initial thought was that doubling the sample rate doesn't buy much,
as you could get the same resolution by changing the beat frequency.
However, it may help control glitching by obtaining the resolution at a
higher beat frequency (greater offset between reference and DUT).
Accurately knowing the duty cycle of the reference clock would be
essential though so that the time of the -ve edge sample was known.
Cheers
Simon
On 22/10/2014 19:09, WarrenS via time-nuts wrote:
The recent discussions about the simple digital mixer got me thinking
about
the performance vs. complexity trade offs when measuring accurate, high
resolution, phase drift differences between two oscillators.
It would seem to me, that using both the positive and negative slope
edges
of the high freq sinewave signal is a better way to go.
Is using just one edge, acceptable for a 'state of the art' Phase drift
measurements?
I am not suggesting the KISS approach is the wrong solution for Simon.
I am questioning if the paper posted, is the best way for CERN to make a
state of the art femtosecond DDMDT?
Here is an extreme example of throwing away useful data for the sake of
simplicity:
When measuring phase drift of a 10 MHz osc using just a 1PPS signal,
19,999,999 other possible data points are being discarded.
Using all possible data points could decrease the noise floor
considerably.
(by ~5,000 to 1)
ws
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