Hi Warren, I arrive a bit late to this discussion, but I hope I can help. I guess the reason for using only one edge is based on the fact that WR is originally designed to measure the phase between a decoded data clock and a system clock. The problem is that this decoded data clock is locked to the incoming data by means of a PFD in the Spartan6/Virtex6 GTP. The PFD normaly only looks at rising edges, so any change in the clock duty cycle will translate in a phase change in the falling edge and not in the rising edge. I am not sure this is really the case, but we certainly had this discussion at the time, but I don't remember if there was any real measurement made.
Cheers, Pablo _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
