On Thu, 05 Mar 2015 09:39:44 -0500
Ben Gamari <[email protected]> wrote:
> Is this just a function of the ring oscillator
> duty cycle being much smaller?
There has been some development on how to do ring oscillators for
TDC applications in recent years. Driven to a large part by the need
for better (longer measure time, higher resolution, better linearity)
TDCs for all digital PLLs (ADPLL).
I haven't read it completely yet, but Straayers dissertation [1]
gives a nice overview of a couple of methods on how to enhance
ring oscillators for the use as a TDC.
I also find [2] quite nice. They use delay lines to both store pulses
and to stretch them. This enables them to work similar to a
pipeline ADC. (I haven't read the paper completely either, so
i might have misunderstood some stuff)
Attila Kinali
[1] "Noise Shaping Techniques for Analog and Time to Digital Converters
Using Voltage Controlled Oscillators", by Straayer, 2008
http://cppsim.org/Publications/Theses/straayer_phdthesis.pdf
[2] "A 9 bit, 1.12ps Resolution 2.5b/Stage Pipelined Time-to-Digital
Converter in 65nm CMOS using Time-Register", by Kim, Yu, Cho, 2014
--
< _av500_> phd is easy
< _av500_> getting dsl is hard
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