Joe,
On 05/19/2015 03:51 PM, Joseph Gwinn wrote:
I'm studying up on how IRIG-B decoder circuits work. What are the good
approaches, the bad approaches, especially in the presence of noise?
(I asked on the NTP group, with little result beyond the C/C++ decoder
software written for the audio channel of a 1990s Sun workstation,
which it ate alive: 50% cpu load.)
Are there decoder ICs available?
The closest to a decoder IC I've found is some FPGA code from a partner
of Microsemi (nee Symmetricom):
..<http://www.microsemi.com/products/fpga-soc/design-resources/partners/semquest>
All marketing and little technical information. I'll have to find out
the details.
I find very little, though I did find one intriguing idea using a
Costas Loop to lock to the 1 KHz carrier, and a posting suggesting
squaring the input signal and phase-locking to the 2 KHz result. Most
recent articles on IRIG decoders come from Chinese sources, mostly in
the AC power industry.
There is a few different approaches for recovering the 1 kHz carrier.
The AM modulation is naturally a bit of a challenge as it will modulate
the slew-rate.
Once the 100 Hz message is recovered, the break-down is relatively
straight-forward.
The question is really, what is the requirement you have and what type
of processing do you think about. A corner of a FPGA will do it.
I prefer the DC level shifted variant of IRIG-B.
Cheers,
Magnus
_______________________________________________
time-nuts mailing list -- [email protected]
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
