God eftermiddag,
On 01/10/2016 11:21 AM, Attila Kinali wrote:
God morgon,
On Sat, 9 Jan 2016 23:01:31 +0100
Magnus Danielson <[email protected]> wrote:
A D-Flipflop is a rather weird mixer. I have not done the calculation,
but i'm pretty sure that the output is not exactly what you'd expect
it from a normal mixer (namely having half the energy at the frequeny
difference and half at the sum).
It's not that wierd. It's a sampler, and thus it acts like a mixer as if
the signal is spikes, which is just another interpretation of the
Nyquist frequency aliasing. Meta-stability however creates an
"interesting" aspect.
Ah right! That also explains my uneasy feeling about it :-)
It's relatively easy to get around metastabilitiy: just add another
couple of D-flipflops in series. Unfortunately, that will only fix
the metastable lingering in-between. It wont fix the edge being at
the wrong time.
Indeed. The second DFF will reduce the noise induced by the
meta-stability. A small average shift in phase due to average
meta-stability time-shift isn't usually a bit problem.
However, it's down-mixing abilities is relatively straight-forward.
A third digital phase-detector is the SR flip-flop. It avoids the 180
degree phase property (really a triangle wave signal) of the XOR, but
give a 360 degree phase sawtooth. This can be helpful in certain lock-up
conditions.
SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?
A straight SR-flipflop. I would have written JK-FF or PFD if I meant it.
Also, as I mentioned the PFD directly after, you could have concluded
that was not what I intended.
A SR-flip-flop with no illegal input states is easy to build from a 74HC00.
The phase-frequency detector of the 4046 and the like has additional
flip-flops to remember slipped cycles and forcing the frequency to
regain that. Those provide a strong frequency lock mechanism with a
phase detector in one.
Interesting... i have to look into the old datasheets.
It's really several SR flip-flops interconnected. It's intended to
simplify design with a "digital" core, it aids in frequency lock as it
pulls the integrator cap in the right direction stronger than the weak
beating does on a distance in frequency difference. This way, you
improve locking time for simple designs. There is other ways to aid the
loop known to the professional.
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Well, you should wire the other parts into passive mode.
That would be a waste of good PCB space ;-)
No. If you add noise through the other parts of the same chip, you will
waste more PCB space to work around it.
Cheers,
Magnus
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