Following my previous note: today I did create simple test installation
using CPLD Xilinx XC2C32A. The project just get input from 50Mhz OSC and
divide it to get 1Hz output to send it to two LEDs and defined clk_out
pin. As I program it - the LEDs was blinking with 1Hz frequency. Which
means its working somehow. ;-)
To simplify it - I was not using D FF at this time (see attached VHDL).
The interesting thing was to look to the report. It said Xilinx CPLD
needs considerable amount of time to deliver the signal to its "ports" :
Constraint: AUTO_TS_F2F
Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clk_out.Q to LED1.D 0.000 3.300 -3.300
clk_out.Q to LED2.D 0.000 3.300 -3.300
prescaler<0>.Q to prescaler<12>.D 0.000 3.300 -3.300
Constraint: AUTO_TS_P2P
Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clk_in to LED1 0.000 3.700 -3.700
clk_in to LED2 0.000 3.700 -3.700
clk_in to clk_out 0.000 3.700 -3.700
Constraint: AUTO_TS_P2F
Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clk_in to clk_in.GCK 0.000 1.300 -1.300
Constraint: AUTO_TS_F2P
Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
LED1.Q to LED1 0.000 2.400 -2.400
LED2.Q to LED2 0.000 2.400 -2.400
clk_out.Q to clk_out 0.000 2.400 -2.400
So, as far I understood, some delays would be expecting. I didn't
measure jitter or anything else yet. But looking to those nanoseconds,
it seems PIC doing better job despite its whole MCU (not just simple
plain CPLD).
===============================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:20:17 01/14/2016
-- Design Name:
-- Module Name: pps - Behavioral
-- Project Name:
-- Target Devices: Xilinx XC2C32A
-- Tool versions: Xilinx ISE
-- Description: Simple frequency divider (divide 50Hz clk, connected to
P1 to 1Hz signal with outputs on P31, P32 and P33
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pps is
Port ( clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
LED1 : out STD_LOGIC;
LED2 : out STD_LOGIC);
end pps;
architecture Behavioral of pps is
signal prescaler : integer range 0 to 49999999 :=0;
signal clk_out_i : std_logic;
begin
gen_clk : process (clk_in)
begin -- process gen_clk
if rising_edge(clk_in) then -- rising clock edge
if (prescaler = 49999999) then
prescaler <= 0;
clk_out_i <= not clk_out_i;
else
prescaler <= prescaler + 1;
end if;
end if;
end process gen_clk;
clk_out <= clk_out_i;
LED1 <= clk_out_i;
LED2 <= clk_out_i;
end Behavioral;
========================================================
--
WBW,
V.P.
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