Hi > On Mar 21, 2016, at 5:37 AM, Tom Van Baak <[email protected]> wrote: > > Hi Chris, > >> In theory what is the best you can do using division of a 10MHz signal. > > Answer: with a 10 MHz PIC the best you can do in theory is +/- 200 ns on > every 32 kHz edge, with no accumulating phase error, and perfect frequency > accuracy for tau 1 s and above. And my divider meets theory. Details on how > the "leap cycle" method works is in the source code: > > http://leapsecond.com/pic/src/pd30.asm > > >> It's really not very good the period of the 32768 hz output will always be >> "off". > > True, whether a PIC or DDS or PLL the period will always be "off", to some > degree, over some interval. So the question is how much is it off and when > does it matter or what's the spec. It's standard phase noise, jitter, and > ADEV stuff. > > I'm not sure of Martyn's goal, but what I use these 10MHz-to-32kHz dividers > for is replacing poor 32 kHz timekeeping with superb 10 MHz-based timekeeping > (e.g., OCXO, Rb, Cs, GPSDO). > > Lots of boards, sensors, loggers, RTC, quartz wall clocks use 32 kHz as a > timebase. They either have a 1-pin input for a 32 kHz clock, or a 2-pin 32 > kHz crystal. Either way, the PIC output can be used to drive the input pin, > and voila! you've now improved the timekeeping by a factor of thousands to > millions. These little PIC's run at 2 to 5 V so its very convenient. > > >> I think the best way is to divide the 10MHz signal by some power of five >> (like 78125) then use that to phase lock your 32768 oscillator. In other >> words use the 10MHz signal to discipline the 32K crystal. > > Right, the extra complexity of a PLL and VCO-tunable 32 kHz tuning fork > crystal (?) would be useful if the end goal were a 32 kHz, low phase noise, > pure sinewave, 50R output, as if a bench instrument. But for driving 32 kHz > CMOS IC timekeeping inputs, the low-jitter square wave from the PIC alone > does the job. >
Also consider the board space and power involved with a 32 KHz PLL. 32 KHz is not an off the shelf/ cheap / stock item for a packaged VCXO. If you start from 10 MHz and build a 32 KHz VCXO, your highest common factor is 128 Hz. That pretty much guarantees some level of spurs on your output with a simple loop. The most likely starting frequency would be 32.768 KHz x 5^N where N is in the 1 to 7 range. 4.096 and 20.48 MHz are better candidates for the VCXO than 32.768 KHz. This of course adds a bit more to the design. Of course you could use a multiplier and drive a DDS chip. Then you could clean the DDS output up with a high frequency narrow band filter. Then you could divide the filter output down to 32 KHz …. Now we’re up to a couple of watts and a fairly big chunk of board space. There also is the minor issue of finding (or building) a filter. Rather than doing it that easily, you could re-design the GPSDO. Build it from scratch with an output that divides directly to 32.768 KHz. It’s just a custom OCXO and a few years of coding. Now we’re up to a bit more power, a bit more size, and a few more parts to fail. There is the minor issue of cost as well….. Yes, there are a lot of exciting ways to do this :) Bob > /tvb > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
