On Wed, 20 Apr 2016 22:44:49 +0000 (UTC)
Bruce Griffiths <[email protected]> wrote:
> Sampling at 4x(10MHz + 1kHz) followed by a digital image reject mixer
> would work better.The front end analog filter only needs to reject
> unwanted nyquist regions, thus it can have a wider bandwidth and low phase
> shift tempco. Its PN noise contribution can also be small. Digital filters
> can be used to reject the undesired spurs.
Yes, the problem with this is that Nick used a ATtiny as uC, which is not
powerfull enough to munch 10Msps of data. Going to something more powerfull
like a Cortex-M3 or so, should allow to do that, though
An alternative would be to use a small FPGA like a Lattice ICE4 or an
Altera MAX and use that to do the sampling, and the PLL. Then using the
PLL/NCO tune word as output once in a while would be very easy to do and
would use very little resources on the uC.
But if you have never done anything with an FPGA that's quite a step up
in design complexity (though once you know how to do it, it's not more
difficult than to use a uC).
BTW: if one would go the FPGA way, i would recommend using a more
powerfull ADC that can do 40Msps (still quite cheap, especially
if only an 8bit variant is used) and clock everything from a 38.8MHz
crystal. Either using a PLL to lock the 38.8MHz oscillator to the 10MHz
OCXO, or using a dual ADC and sample both reference and OCXO at the same
time.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
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