utilizing rising and falling edges makes the circuit output signal duty
cycle sensitive to the input signal's duty cycle, and therefore the
harmonic content will vary with the input duty cycle variation.
73
KJ6UHN
Alex
On 6/8/2016 9:47 AM, Richard (Rick) Karlquist wrote:
The URL you cited doesn't have the schematic in any obvious
place. However, using both edges of the clock to supposedly
result in 50% duty cycle output depends on having 50%
duty cycle at the input. If you have differential logic
like ECL, this can be realistic. Single ended logic,
questionable.
The other issue is that the divider can start up in any
one of 3 phases with respect to any other frequency
dividers in your system, unless you do something to
synchronize the various dividers.
This is probably old hat to most readers of time-nuts, but
I just wanted to mention it in case some were unaware
of it.
Rick
On 6/8/2016 6:55 AM, Nick Sayer via time-nuts wrote:
I’m contemplating trying my GPS board with an FE-405B. That’s a
different kettle of fish, but at the end of that, if I’m successful,
one of the goals would be to be able to use it for the external
reference of my 53220A. Unfortunately, 15 MHz isn’t one of the
options - only 1, 5 and 10.
So I did some googling and found a divide-by-3 circuit using
flip-flops, and then designed a board for it:
https://oshpark.com/shared_projects/jxXp7wYM
The circuit uses 3 D flip-flops and 3 NOR gates and has a 50% duty
cycle output that’s 1/3 the frequency of the input. The OSHPark
project has a pointer to the original blog post that has a schematic.
The only difference between their schematic and mine is that in
theirs, the third flip-flop has an inverted clock input. The third
NOR gate inverts the clock to achieve that in mine (also one
flip-flop and one NOR gate are unused and have the inputs tied high).
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