On Sun, June 12, 2016 10:50 pm, John Swenson wrote: > I'm just doing phase noise measurements of digital clocks (square waves) > so it seems to me I don't need some of the circuitry in the TimePod, in > particular the digitally controlled RF attenuators and the ADCs > themselves. My idea is to use LVPECL flip-flops to sample the DUT and > reference clocks, convert the differential outputs to CMOS and feed the > FPGA inputs from that. Yes you loose AM noise riding on top of the > square wave, but is that really necessary for just square wave phase > noise measurements?
Are the FPGA inputs low enough noise for that? With an ADC the time resolution is a combination of clock noise and input noise, for most high quality ADC the effective time resolution you can achieve by analyzing the output data stream is much higher than the resolution of the clock period. Can you achieve similar with just a single bit quantizer based on the FPGA CMOS inputs? -- Chris Caudle _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
