it is a way to use a carrier fc to make one SSB signal with fm
modulation frequency, use just the side-band, , which have a frequency
of fc + fm = fR, [fR/fc is a function of the SSB modulator carrier
suppression capability,] fm could be from less than 1/2 fc any
frequency to zero, if it is zero fR =f c. With fm is not zero, the phase
of fR will advance relative to fc as long as fm is not zero if fm
becomes zero the advance will stop.
The generation of a very small frequency offset will need fm = the
offset frequency
To "clean up" the resulting fR, a PLL could be locked to it, which could
look to one single frequency only [with very narrow tuning range
oscillator, perhaps a a tunable crystal and very narrow loop filter
[just to let pass fm ]
since oscillators are by definition amplifiers with infinite high gain
that PLL could look into fc!
Attila I don't know anything about any patent, but I developed that kind
of system for video colour performance analyzing system in the "past
century".
73
KJ6UHN
Alex
On 7/29/2016 9:23 AM, Attila Kinali wrote:
On Fri, 29 Jul 2016 00:26:07 +0000 (UTC)
Bruce Griffiths <[email protected]> wrote:
Diophantine Frequency Synthesizer Design for Timekeeping Systems
I quickly went over the papers people have pointed me at. Without
having gone through all the math, the idea for choosing the PLL values
looks neat. The 2-cascaded synthesizer is also the one used by Spectratime
for their FemtoStepper, which bring us back to the question: How do they
achieve phase steps? I see how offset frequencies are generated (with
arbitrary small step sized), but I do not see how this can be turned
in fine resulution phase steps when using PLL's as the controlling elements.
Discusses a diophantine synthesiser.Note Sotiriadis' work on diophantine
numbers and frequency synthesis appears to be a rehash of an old Patent
perhaps due to a lack of competent searching for prior art.This issue was
discussed on the list some time ago,
Which patent are you refering to?
Attila Kinali
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