Hi Bryan,
No ! Assuming you mean R1/R2/C1/C2 of the Miller schematic, those
values are already set for the comparison frequency (10KHz) of the PLL
phase comparator (U2).
Bill....WB6BNQ
Bryan _ wrote:
Hello:
I have been following the Jim Miller simple GSDO build project at http://www.jrmiller.demon.co.uk/projects/ministd/frqstd0.htm I have a few OCXO's kicking around, but wondering what would the appropriate components be for for R1,R2, C1, C2 to provide the PLL filter. I assume the PLL filter needs to be designed to accommodate a specific oscillator specifications, or maybe it doesn't really matter and can use the default values in the schematic?.
Was also considering using a picdiv instead of the 2- 74HC390, not sure if that would be an advantage or disadvantage in terms of operating performance?
Cheers
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