Hi Some quick hints:
1) You need a way to digitize the phase input with adequate resolution. If you have a 1 second period and want 1 ns, you need a way to digitize at a 1:1,000,000,000 sort of level. That’s in the 30 bit range so a simple ADC isn’t going to do it alone. 2) You need a way to digitize the control output. If you have a +/- 2 ppm EFC range and a 16 bit DAC you get a LSB step around 4/65,000 = 6x10^-8. If you are after < 1x10^-9, 16 bits isn’t going to get you there all by it’s self. 3) In the middle of the two, you have a loop gain, an integrator time constant, and a bit of phase shift. That plugs into the standard equations to come up with a solution (along with the normal sensitivities that drive any PLL). Yes, there are a lot of weird issues to deal with, but conceptually there isn not a lot to it. Bob > On Mar 21, 2017, at 7:25 PM, James Peroulas <[email protected]> wrote: > > Thanks for the hints and references everyone. I'll dig in and possibly come > back with some more questions. > > BR, > James > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
