On 01/29/2018 04:54 PM, Chris Caudle wrote:
On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:
The close-in phase noise is quite amazing, but the floor is much worse
than in free-run mode.
That phase noise plot doesn't look quite right, what PLL bandwidth did you
set?
Sorry for the earlier null reply. I just used the settings that the
ClockBuilder software came up with (which IIRC don't offer any choices
about loop bandwidth in the "wizard"). I haven't yet dug into the
register options, but I'm sure that there are ways to optimize.
John
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