but as I wrote a while ego ADI has a bit different chip which is free of
dead zone and much faster, I used it for low phase-noise clock generator
for 3,1Gb/s fiber optic systems of C-Cor/Comlux in the end of the past
century, now I am on vacation and do not have my engineering note books
with me, but 1) I already posted it in the past 2) I will post it again
after I returned home,
73
KJ6UHN
On 5/6/2018 1:03 AM, Charles Steinmetz wrote:
See below for further information on working with the 4046/7046/9046
PLL families, including must-have design tools for anyone designing
with these devices.
I wrote:
The "flaw" in the 4046 is a dead zone around zero error in Phase
Comparator 2 (the PC one generally uses).
Magnus responded:
It is very bad indeed. Someone chose to use the 4046 to lock up a 155,52
MHz VCXO to a 8 kHz reference, using a 4046 as a core. The charge-pump
was then "accelerated" with a supposedly better charge-pump with a ton
of passives. Turns out that the dead-band was still there to haunt the
designers. The 155,52 MHz was further multiplied to become the 2,48832
Gb/s clock, and as they measured this they had problems with the
jitter/wander of it
Of course the dead zone was still there -- it is built into the
4046/7046 phase comparator, and nothing you do after-the-fact can
eliminate it (but see below re: linearizing the 4046/7046 phase
comparator). Most of what is wrong with the circuit you describe above
is simply bad system design, not any fault of the 4046.
While it is true that some people call the PC2 output of the 4064 a
"charge pump," as a voltage source it is, at best, a very poor one.
The 9046 has a real, current-mode charge pump with tri-state outputs.
The attached charts show the difference in linearity [1].
There are tricks one can pull to linearize the PC2 output of a 4046 or
7046. In particular, (i) injecting current into the PC2 output node
biases the detector away from the dead zone at the price of a static
phase error, and (ii) instead of using a passive RC filter, run the
PC2 output through the resistor to the virtual-ground input of an
active filter, which effectively turns the PC2 voltage output into a
bipolar current output. Still, however, the 4046/7046 PC2 cannot
overlap positive and negative steering pulses as the 9046 PC2 can, and
the 9046 thresholds are established by a real voltage reference, so
the 9046 will always be better than the best that can be done with a
4046 or 7046.
I do not use 4046-type devices very often, but ever since the 9046
became available I have used it exclusively in preference to the 4046
and 7046.
Best regards,
Charles
[1] The attached charts are taken from the Philips CMOS PLL
Designer's Guide (1995), which is an absolute must-have for anyone
designing with the 4046/7046/9046 PLL families. List member Daniel
Mendes pried the Guide and supporting files out of Philips a couple of
years ago, and list member Oz from DFW hosts them on his site. I
cropped the pages of the Design Guide to eliminate the large white
borders and re-posted it all as a zip file to Didier's site:
<http://www.ko4bb.com/getsimple/index.php?id=download&file=03_App_Notes_-_Proceedings/74HC4046_7046_9046_CMOS_PLL_design_guide_and_files_Philips_1995.zip>.
Enjoy!
---
This email has been checked for viruses by AVG.
http://www.avg.com
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
